Lesson 4 of 5Electronics and Digital Logic

Unit 4 · Lesson 4 of 5

Logic Gates and Truth Tables

How voltages become true and false, the seven gates that combine them, and how to describe any circuit with a truth table.

4 min read10 practice questionsInteractiveAsk AI about this →

Key things to remember

1In 5 V logic, above ~2.0 V is logic 1 and below ~0.8 V is logic 0.
2AND needs every input true; OR needs at least one; XOR needs the inputs to differ.
3A bubble on a gate's output means invert: NAND is AND then NOT.
4n inputs give $2^{n}$ truth-table rows.
5Half adder: SUM = A ⊕ B, CARRY = A · B.
6NAND and NOR are universal — any logic function can be built from either alone.
7Never leave a logic input floating; tie unused inputs high or low.

Digital electronics takes a continuous voltage and forces it into two categories. In a 5 V system, anything above about 2.0 V is read as logic 1 and anything below about 0.8 V as logic 0. The band between is undefined and a well-designed circuit never lingers there. This deliberate throwing away of information is what makes digital circuits robust: a signal degraded by noise still lands in the right category, and gets cleanly regenerated by the next gate.

Fig 1The five two-input gates, all four input combinations.

The gates

Gate	Boolean	Plain English	Output is 1 when…
AND	Y = A · B	both	every input is 1
OR	Y = A + B	either	at least one input is 1
NOT	Y = A′	opposite	the input is 0
NAND	Y = (A·B)′	not both	NOT every input is 1
NOR	Y = (A+B)′	neither	all inputs are 0
XOR	Y = A ⊕ B	different	the inputs differ
XNOR	Y = (A⊕B)′	same	the inputs match

The bubble means invert

NAND, NOR, XNOR and NOT are all drawn as the plain gate with a small circle on the output. That bubble always means "then invert". So if you know AND you already know NAND — work out the AND result and flip it.

Loading interactive…

Toggle the inputs and watch the matching truth-table row light up.

Building and reading a truth table

A truth table lists every possible combination of inputs and the output for each. With n inputs there are 2ⁿ rows — 4 rows for two inputs, 8 for three, 16 for four. Write the input columns in counting order (00, 01, 10, 11) so you cannot accidentally miss a combination, then add an intermediate column for each gate in the circuit and fill it before attempting the final output.

Fig 2A half adder: XOR gives the sum bit, AND gives the carry.

The half adder is worth understanding because it is where logic gates stop being abstract. Adding two bits gives 0+0=0, 0+1=1, 1+0=1, and 1+1=10 — a sum bit of 0 and a carry of 1. Look at the sum column: it is exactly XOR. Look at the carry column: it is exactly AND. Two gates perform binary addition, and chaining full adders (which also accept a carry in) builds the adder inside every CPU's ALU.

Combinational circuits

A combinational circuit's output depends only on its inputs right now, with no memory of what came before. Every circuit in this topic is combinational. Working out its behaviour is always the same procedure: label the output of every gate, build a truth table with one column per label, fill the columns left to right in the order the signals flow, and read off the final column.

From a sentence to a circuit

"The alarm sounds if the door is open AND the system is armed, unless the override is pressed." Name the variables: D, A, V. Translate the connectives directly: AND is ·, OR is +, "unless"/"not" is a prime. That gives

Alarm = D \cdot A \cdot V^{'}

. Then draw one gate per operator.

Real chips

The classic 7400-series chips put several gates in one 14-pin package: a 7408 holds four AND gates, a 7432 four ORs, a 7404 six inverters, and the 7400 four NANDs. Pin 14 is supply and pin 7 is ground on almost all of them. Every unused input must be tied to a defined level, because a floating CMOS input drifts, oscillates and wastes power — it does not politely sit at zero.

Why NAND is called a universal gate

Any logic function at all can be built from NAND gates alone. A NAND with both inputs tied together is a NOT. Two NANDs make an AND. Three make an OR. Chip fabrication is cheaper when one gate type is used throughout, so real silicon is full of NAND and NOR structures rather than the tidy AND/OR of a textbook diagram. NOR is universal for the same reason.

Worked examples

Reveal one step at a time and try to beat it to the next line.

Example 1

Build the complete truth table for

Y = (A + B) \cdot C^{'}

Example 2

A machine must start only when the guard is closed (G), the operator presses start (S), and the emergency stop is NOT pressed (E). Write the Boolean expression and list the gates needed.

Example 3

Show that a NAND gate with both inputs tied together behaves as a NOT gate.

Where marks get lost

Mixing up NAND and NOR. NAND is 0 only when both inputs are 1; NOR is 1 only when both are 0.
Treating XOR as OR. XOR gives 0 when both inputs are 1.
Missing rows in a truth table. n inputs always need exactly $2^{n}$ rows — list them in counting order.
Leaving unused logic inputs floating. A floating CMOS input oscillates and can destabilize the whole chip.
Reading the Boolean + as ordinary addition. $1 + 1 = 1$ in Boolean algebra, because it means OR.
Forgetting that AND binds tighter than OR, so $A + B \cdot C$ means $A + (B \cdot C)$ .

Flashcards 10

When is an AND gate's output 1?

When is an OR gate's output 1?

When is a NAND gate's output 0?

When is a NOR gate's output 1?

+ 6 more

Practice

A NAND gate has inputs A = 1 and B = 0. What is the output?

Which gate outputs 1 only when its two inputs are different?

How many rows does the truth table of a circuit with 5 inputs have?

rows

In a half adder, which gate produces the CARRY output?

What is the output of a NOR gate when both inputs are 0?

Evaluate

Y = A \cdot B + C

when A = 1, B = 0, C = 1.

Match each gate to its behaviour.

AND

NOR

XNOR

Why must an unused input on a CMOS logic chip be tied high or low?

Order these steps for analyzing a multi-gate combinational circuit.

1List all $2^{n}$ input combinations in counting order
2Read the final column as the circuit's output
3Fill in one column per gate, following the signal flow
4Label the output of every gate

A safety circuit must run only when

G \cdot S \cdot E^{'} = 1

. The emergency stop E is pressed (E = 1). What is the output?

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